1. Field of the Invention
This invention relates to a carrier recovery phase-locked loop for recovering a carrier from a time-divided received wave as in the case of a modulated wave in a time division multiple access scheme and more particularly to a carrier recovery phase-locked loop suitable for recovering a carrier from a digitized quadrature phase shift keying (QPSK) modulated wave.
2. Description of the Related Art
In the field of satellite communications, various multiple access schemes have been proposed from the standpoint of effective utilization of electric waves. At present, the TDMA (Time Division Multiple Access) scheme is the most promisingly applicable scheme. In the TDMA scheme, the modulated wave takes the form of a burst signal on the time axis. When TDMA type multiple access is to be effected using digitized quadrature phase shift keying, it is necessary for the receiver to recover a carrier each time a burst signal arrives. To meet this requirement, in the transmitter a preamble is added as the heading to each burst-like transmission signal and in the receiver, the carrier recovery, timing recovery and automatic gain control are synchronized within an interval of time for reception of the preamble.
In order to improve channel utilization, the duration of the preamble added as the heading to the burst-like signal is required to be short and the carrier is therefore required to be recovered at high speeds.
Further, because of the desirability of a compact antenna of small diameter for earth stations use, the recovery loop is desired to operate even with low C/N ratios (Carrier to Noise Ratios).
Furthermore, in a satellite channel in which carriers of high frequencies are used, the difference in frequency between carriers for individual received burst-like signals is large and the difference in frequency between a carrier of a received signal and the reference carrier of the receiver is also large.
For recovery of the carrier, a PLL (Phase-Locked Loop) circuit is widely used but the aforementioned requirements are contradictory, in general, to the operational performance of the PLL circuit.
As a prior art reference which can recover a carrier from a digitized burst-like phase shift keying modulated wave while maintaining minimization of the synchronization time, there is available, for example, JP-A-50-24062. In this prior art reference, a carrier corresponding to a received carrier is recovered by means of a narrow band filter substituting for a PLL circuit so that during synchronization, an input modulated wave is inverse-modulated with a fixed pattern corresponding to its preamble to ensure high speed pull-in at the heading of the burst signal.
However, the inverse-modulation of this prior art is to cancel phase shifts by using modulation components so as to provide a non-modulated wave, and therefore, the inverse-modulation must be carried out by using a pseudo-demodulation signal generated in advance of the synchronization. Accordingly, hardware for this purpose is additionally provided, raising a problem that the amount of hardware is increased. On the other hand, as the frequency offset between a received carrier and the reference carrier increases, there results a phase offset during the synchronization. To prevent the phase offset, the additional provision of an AFC (Auto-Frequency Control) loop is needed which bottlenecks realization of simplified hardware and low power consumption. In addition, the prior art loop is difficult to digitize.